Area Efficient Level Sensitive Flip-Flops – A Performance Comparison

Abstract

Due to increased demand of portable and battery operated devices, ultra-low power and high speed devices with less area requirement are important nowadays. Latch is the basic element for all the sequential circuits. This paper presents comparison of various circuits of D latch on the basis of power consumption, area efficiency and delay. Basically in these latches transmission gates are replaced by pass transistors to reduce the transistor count. Comparison results indicate that latch design with least transistor count is the best choice for portable applications.

Keywords: area efficient, latch, sub-threshold region, pass transistor, low power, level sensitive flip-flops, flip-flops.