Performance Analysis of SRAM Cell Using DG-MOSFETs

Mukeem Ahmad


As the technology in electronic circuits is improving, the complexity in these circuits also increases. The complexity in the circuits leads to the need of that type of circuits which are portable and fast circuits. The portability in the electronic circuits is achieved by the use of battery. So we have to develop such sort of circuits that use very less power. The main focal point in designing a high performance digital system such as microprocessors and various Digital signal Processors is given to low power design. The key part of any digital system is its memory unit. It is not possible to design a digital system without memory. So we can say that memory is the main part which employ the highest power in the system. The most used memory cell in the digital systems is the SRAM cells. They are the static RAM cells. Low-power Random Access Memory (RAM) has seen a remarkable and rapid progress in power reduction. The high density and low power SRAMs are needed for application such as hand held devices, laptops, notebooks, IC memory card because of the fact that they are portable devices and uses batteries for power source so they must consume power as low as possible. As the semiconductor technology scales down, the read stability and write capacity of a static random-access memory (SRAM) cell are degraded because of the increased mismatch among its transistors.  In sub-threshold conduction, leakage current is main culprit to increased power dissipation and degradations. There are scale issues which arise in nanometer range of operation. These issues cannot be resolved in conventional MOS transistors.  DG-MOSFETs are one of the attractive candidates to reduce these problems in extremely nano-scaled devices. Further SRAM   cell are chief component for today’s electronic industry. This report presents a novel CMOS four and two-transistor SRAM cell for very high density and low power embedded SRAM applications as well as for stand-alone SRAM applications.

Keywords: SRAM, Tanner 16.0, 4T&2T SRAM Cell

Full Text: PDF
Download the IISTE publication guideline!

To list your conference here. Please contact the administrator of this platform.

Paper submission email:

ISSN (Paper)2224-5774 ISSN (Online)2225-0492

Please add our address "" into your email contact list.

This journal follows ISO 9001 management standard and licensed under a Creative Commons Attribution 3.0 License.

Copyright ©