Design of Low Offset and High Speed CMOS Comparator for Analog to Digital Converter

Abstract

In today’s world everything is digitized but nature is analog, so it is necessary to have such a device which converts analog signal into digital and for this analog to digital converter is required. Now a day’s ADC’s require lesser power, better slew rate, high speed and less offset. Performance limiting component for ADC’s are amplifiers and comparators in which comparator is the most important.This paper presents the design of low offset low power dissipation and high speed  comparator. The proposed comparator consists of a preamplifier stage, decision stage and self biased output buffer stage. The proposed design uses a low power current mirror circuitry for providing a highly biased current. The circuit is designed using 90nm CMOS process for a supply voltage of 1V and reference voltage of 0.5V and power consumption is approximately 300?W.

Keywords: CMOS Comparator, Current Mirror, Pre Amplifier, Output Buffer