Different SRAM Cells Using Low Power Reduction Techniques

Abstract

With increasing technology, usage of SRAM Cells has been increased to large extent while designing the system on-chips in CMOS technology. Power consumption and the speed are the major factors of concern for designing a chip along with the leakage power. The consumption of power and speed of SRAMs are some important issues among a number of factors that provides a solution which describes multiple designs that minimize the consumption of power and this article is also based on that. This article presents the simulation of 6T, 8T and 9T SRAM cells using low power reduction techniques and develops a modified model that provides the consumer with a product that costs less and having reduced power delay product. All the simulations have been carried out on 90nm at Tanner EDA tool. The entire circuit verification is done using the Tanner tool.

Keywords: CMOS Logic, SRAM and VLSI.