Design Optimization of Double Gate Based Full Adder
Abstract
Full adder is the essential block of circuit of arithmetic’s found in microprocessor and microcontroller in ALU (arithmetic and logic unit). Improving the performance of the adder is very important for up gradation the performance of digital circuit of electronics in which adder is utilized. The main aim of designing of arithmetic circuit is the power consumption. In an arithmetic circuit, the adder is a critical module for operation of addition and also the core for many operations related to arithmetic. Therefore it is obliged to decrease the consumption of power of adder circuit so as to diminish the consumption of the module related to arithmetic. In this paper, a review of double gate based full adder is presented. Various works on this research work which is already available is presented and also problem related to them are presented.
Keywords: DG-MOSFET, ALU, XOR, Full Adder,PTI, GDI, Diffused Gdi,Finfet, ELK, Power Grating , Stacking .
To list your conference here. Please contact the administrator of this platform.
Paper submission email: ISDE@iiste.org
ISSN (Paper)2222-1727 ISSN (Online)2222-2871
1Please add our address "contact@iiste.org" into your email contact list.
This journal follows ISO 9001 management standard and licensed under a Creative Commons Attribution 3.0 License.
Copyright © www.iiste.org