Designing of Different High Efficiency Diode Clamped Multilevel

Abstract

This research work is aimed at designing of high efficiency multilevel diode clamped inverter. It would cover diode clamped multilevel inverter with particular reference to the comparison of high level and low level inverter using efficient modulation method (sinusoidal pulse width modulation). The main theme of this research is to obtain a pure sinusoidal waveform of high quality having minimum harmonics that can be utilized for both industrial purposes and to sensitive domestic loads. The proposed design besides considering high quality of the output waveform of multilevel diode clamped inverter, the problems regarding multilevel inverter design has been given more consideration high voltage stresses across switching devices. The voltage stresses issues have been resolved with DC link voltage equally distributed among capacitors in multilevel inverter. Simulation results for different level inverters both low level (5, 7, 9, level) and high levels (11, 13, 15) are used as a reference. The proposed design resulted in reduced total harmonic distortion thus eliminating the harmonics in the output waveform to a greater extent resulting in pure sine waveform output. This resulted in reduction in overall losses and elimination of voltage balancing problems in high level diode clamped inverter.

Keywords: Hormonics, Clamping, Inverter, Pulse Width Modulation, Sinusoidal Pulse Width Modulation (SPWM).