Proposed Thermal Circuit Model for the Cost Effective Design of Fin FET

Abstract

The Complementary metal-oxide-semiconductor (CMOS) device has been rapidly evolving and its size has been drastically decreasing ever since it was first fabricated in 1960 [Us Patent 3,356,858: 1967]. The substantial reduction in the CMOS device size has led to short channel effects which have resulted in the introduction of Fin Field Effect Transistor (FinFET), a tri-gate transistor built on a silicon on insulator (SOI) substrate. Furthermore, due to the geometry of the FinFET the severity of the heating problem has dramatically increased. Self-heating in the 3-dimensional FinFET device enhances the temperature gradients and peak temperature, which decrease drive current, increase the interconnect delays and degrade the device and interconnect reliability. In this work we have proposed a methodology to develop an accurate thermal model for the FinFET through a rigorous physics-based mathematical approach. A thermal circuit for the FinFET will be derived from the model. This model will allow chip designers to predict interconnect temperature which will lead them to achieve cost-effective design for the FinFET-based semiconductor chips.

Keywords: Bulk CMOS, SOI CMOS, FinFET, Thermal heating.