Low Power &High Speed Domino XOR Cell

Abstract

The XOR gate plays an important role in digital system like arithmetic circuits and encryption circuits. This paper proposes a domino XOR cell designed using hybrid domino logic technique. The proposed design demonstrates better power consumption, better delay and hence better power delay product (PDP) at varying supply voltages, frequency and temperature when compared with existing design along with full voltage swing. All simulations are performed on 90nm standard model on Tanner EDA tool version 13.0.

Keywords: Domino, low power, PDP and XOR.