Single Edge Triggered Static D Flip-Flops: Performance Comparison

Abstract

Due to fast growth of portable devices, power consumption and timing delays are the two important design parameters in high speed and low power VLSI design arena. In this paper we presents the comparison of single edge triggered static D flip-flop designs to show the benefit of power consumption ,delay and power delay product on the basis of area efficiency.

Keywords: Single edge triggered flip-flops, super-threshold region, parasitic capacitance, transmission gate