Novel Low Power and Low Transistor Count Flip-Flop Design with High Performance

Abstract

The paper proposed a new design of static SET flip-flop for low power applications. In this work, comparative analysis of existing architecture for flip-flops along with the proposed design is made. The comparison is done on the basis of power and power delay product, transistor count is also included. Due to continuous increase in integration of transistors and growing needs of portable equipments, low power design is of prime importance. The proposed design has the best power and the second best PDP than the existing architectures. Proposed FF has the least transistor count hence reducing the manufacturing cost and area. All simulations are performed on TSpice using BSIM models in 130 nm process node. The simulation results show that for all supply voltages, proposed FF has the best power consumption, second best PDP and the lowest transistor count. So this design is best suited for low power and high performance portable applications.

Keywords: Transmission Gate, Short circuit current, Edge Triggered, Optimization