Realization Of An 8-bit Pipelined Microprocessor in Verilog HDL

Abstract

Pipelining is a technique of decomposing a sequential process into sub-operations, with each sub process being divided segment that operates concurrently with all other segments. A pipeline may be visualized as a collection of processing segments through which binary information flows. Each segment performs partial processing segments dictated by the way the task is partitioned. The result obtained in one segment is transferred to subsequent segments in each step. The final result is obtained after the data has passed through all segments.This paper develops a code for the implementation of an 8-Bit microprocessor which implements instruction pipelining. After synthesis, an FPGA realization may be obtained . Simulation using Xilinx and ModelSim also produces favourable results which showcase the speedup (in terms of time) to carry out a program as compared to a non-pipelined version of this microprocessor.

Keywords:Pipelining, Segments,sysnthesis,realization,FPGA,microprocessor