1-Bit Full Adder Circuit using XOR-XNOR Cells with Power and Area Optimization

Suman Jhajharia


This paper revel a realization of a superior circuit design of 1 bit full adder. The circuit is planned and implemented by using planar DG –MOSFETs at 45 nm technology. In CPU, arithmetic logic unit (ALU) is the core heart.   The adder cell is the important and necessary unit of an ALU. In the present paper, an improved 1-bit full adder circuit is proposed that consumes lower power and reduced number of transistors. The proposed adder circuit consists of 9 transistors and called as 9-T adder cell.  The planar DG-MOSFETs are new emerging transistors which can work n nanometer range and overcome the short channel effects. The simulation of proposed circuit is done in tanner tool version 13.0 using level 54 model files. The simulation is done to compare power, power delay product with supply voltage. The result is also checked at room temperature. This circuit performance of the proposed circuits compared with other reported circuits in literatures and it is seen approximately more than 99.9% reduction in power consumption.

Keywords: Low power; Area Efficent; Full Adder; GDI; Multiplexers

Full Text: PDF
Download the IISTE publication guideline!

To list your conference here. Please contact the administrator of this platform.

Paper submission email: JETP@iiste.org

ISSN (Paper)2224-3232 ISSN (Online)2225-0573

Please add our address "contact@iiste.org" into your email contact list.

This journal follows ISO 9001 management standard and licensed under a Creative Commons Attribution 3.0 License.

Copyright © www.iiste.org